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1 tm file number 4151.7 HC5526 itu co/pabx slic with low power standby the HC5526 is a subscriber line interface circuit that is compliant with ccitt standards. enhancements include immunity to circuit latch-up during hot plug and absence of false signaling in the presence of longitudinal currents. the HC5526 is fabricated in a high voltage dielectrically isolated (di) bipolar process that eliminates leakage currents and device latch-up problems normally associated with junction isolated (ji) ics. the elimination of the leakage currents results in improved circuit performance for wide temperature extremes. the latch free bene? of the di process guarantees operation under adverse transient conditions. this process feature makes the HC5526 ideally suited for use in harsh outdoor environments. features di monolithic high voltage process programmable current feed . . . . . . . . . . . 20ma to 60ma programmable loop current detector threshold and battery feed characteristics ground key and ring trip detection compatible with ericsson s pbl3764 thermal shutdown on-hook transmission wide battery voltage range . . . . . . . . . . . . .-24v to -58v low standby power meets ccitt transmission requirements ambient temperature range . . . . . . . . . . . -40 o c to 85 o c applications on-premises (ons) key systems pbx related literature - an9537, operation of the hc5513/26 evaluation board block diagram ordering information part number temp. range ( o c) package pkg. no. HC5526cm 0 to 70 28 ld plcc n28.45 ringrly dt dr tip ring hpt hpr v bat v cc v ee agnd bgnd v tx rsn e0 e1 c1 c2 det ring relay driver 4-wire interface vf signal path ground key detector loop current detector r dc rsg bias digital multiplexer ring trip detector 2-wire interface r d data sheet october 2000 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright ?intersil corporation 2000
2 absolute maximum ratings thermal information operating temperature range . . . . . . . . . . . . . . . . -40 o c to 110 o c power supply (-40 o c t a 85 o c) supply voltage v cc to gnd . . . . . . . . . . . . . . . . . . . . 0.5v to 7v supply voltage v ee to gnd. . . . . . . . . . . . . . . . . . . . . -7v to 0.5v supply voltage v bat to gnd . . . . . . . . . . . . . . . . . . . -70v to 0.5v ground voltage between agnd and bgnd . . . . . . . . . . . . . -0.3v to 0.3v relay driver ring relay supply voltage . . . . . . . . . . . . . . . . . . . . . 0v to 20v ring relay current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50ma ring trip comparator input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v bat to 0v input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5ma to 5ma digital inputs, outputs (c1, c2, e0, e1, det) input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0v to v cc output voltage ( det not active) . . . . . . . . . . . . . . . . . 0v to v cc output current ( det) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma tipx and ringx terminals (-40 o c t a 85 o c) tipx or ringx voltage, continuous (referenced to gnd) v bat to 2v tipx or ringx, pulse < 10ms, t rep > 10s . . . . . .v bat -20v to 5v tipx or ringx, pulse < 10 s, t rep > 10s . . . . v bat -40v to 10v tipx or ringx, pulse < 250ns, t rep > 10s. . . . v bat -70v to 15v tipx or ringx current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70ma esd rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500v thermal resistance (typical, note 1) ja ( o c/w) 28 lead plcc package. . . . . . . . . . . . . . . . . . . . . . 53 continuous dissipation at 70 o c 28 lead plcc package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5w package power dissipation at 70 o c, t < 100ms, t rep > 1s 28 lead plcc package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4w derate above . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 o c plcc package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.8mw/ o c maximum junction temperature range. . . . . . . . . . -40 o c to 150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (plcc - lead tips only) die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . 543 transistors, 51 diodes caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. typical operating conditions these represent the conditions under which the part was developed and are suggested as guidelines. parameter conditions min typ max units case temperature -40 - 100 o c v cc with respect to agnd 0 o c to 70 o c 4.75 - 5.25 v v ee with respect to agnd 0 o c to 70 o c -5.25 - -4.75 v v bat with respect to bgnd 0 o c to 70 o c -58 - -24 v electrical speci?ations t a =0 o cto70 o c, v cc =5v 5%, v ee = -5v 5%, v bat = -28v, agnd = bgnd = 0v, r dc1 =r dc2 = 41.2k ? , r d = 39k ? , r sg = , r f1 = r f2 = 0 ? , c hp = 10nf, c dc = 1.5 f, z l = 600 ? . parameter conditions min typ max units overload level 1% thd, z l = 600 ? , (note 2, figure 1) 3.1 - - v peak longitudinal impedance (tip/ring) 0 < f < 100hz (note 3, figure 2) - 20 35 ? /wire figure 1. overload level (two-wire port) figure 2. longitudinal impedance tip 27 v tx 19 ring 28 rsn 16 i dcmet r t r rx e rx r l v tro 600k ? 300k ? 600 ? 23ma e l v t c 0 < f < 100hz v r lz t = v t /a t lz r = v r /a r 1v rms 300 ? 300 ? 2.16 f tip 27 v tx 19 ring 28 rsn 16 r t r rx 600k ? 300k ? a t a r HC5526 3 longitudinal current limit (tip/ring) off-hook (active) no false detections (loop current), lb > 45db (note 4, figure 3a) - - 20 ma peak / wire on-hook (standby), r l = no false detections (loop current) (note 5, figure 3b) --5ma peak / wire figure 3a. off-hook figure 3b. on-hook figure 3. longitudinal current limit off-hook longitudinal balance longitudinal to metallic ieee 455 - 1985, r lr , r lt = 368 ? , 0.2khz < f < 4.0khz (note 6, figure 4) 53 60 - db longitudinal to metallic r lr , r lt = 300 ? , 0.2khz < f < 4.0khz (note 6, figure 4) 53 60 - db metallic to longitudinal fcc part 68, para 68.310 0.2khz < f < 1.0khz 50 55 - db 1.0khz < f < 4.0khz (note 7) 50 55 - db longitudinal to 4-wire 0.2khz < f < 4.0khz (note 8, figure 4) 53 60 - db metallic to longitudinal r lr , r lt = 300 ? , 0.2khz < f < 4.0khz (note 9, figure 5) 50 55 - db 4-wire to longitudinal 0.2khz < f < 4.0khz (note 10, figure 5) 50 55 - db figure 4. longitudinal to metallic and longitudinal to 4-wire balance figure 5. metallic to longitudinal and 4-wire to longitudinal balance 2-wire return loss c hp = 20nf 0.2khz to 0.5khz (note 11, figure 6) 25 - - db 0.5khz to 1.0khz (note 11, figure 6) 27 - - db 1.0khz to 3.4khz (note 11, figure 6) 23 - - db electrical speci?ations t a =0 o cto70 o c, v cc =5v 5%, v ee = -5v 5%, v bat = -28v, agnd = bgnd = 0v, r dc1 =r dc2 = 41.2k ? , r d = 39k ? , r sg = , r f1 = r f2 = 0 ? , c hp = 10nf, c dc = 1.5 f, z l = 600 ? . (continued) parameter conditions min typ max units r dc2 41.2k ? r dc1 41.2k ? c dc 1.5 f e l -5v 39k ? 368 ? 368 ? c 2.16 f a tip 27 rsn 16 ring 28 r dc 14 det r d a r dc2 41.2k ? r dc1 41.2k ? c dc 1.5 f e l -5v 39k ? 368 ? 368 ? a tip 27 rsn 16 ring 28 r dc 14 det r d c 2.16 f c 2.16 f a r t r rx e l v tr 600k ? 300k ? c r lt r lr v tx 2.16 f tip 27 v tx 19 ring 28 rsn 16 r t r rx e tr v l 600k ? 300k ? c r lt r lr e rx 300 ? 300 ? 2.16 f tip 27 v tx 19 ring 28 rsn 16 HC5526 4 tip idle voltage active, i l = 0 --4- v standby, i l = 0 -<0- v ring idle voltage active, i l = 0 - -24 - v standby, i l = 0 - >-28 - v 4-wire transmit port (v tx ) overload level z l > 20k ? , 1% thd (note 12, figure 7) 3.1 - - v peak output offset voltage e g = 0, z l = (note 13, figure 7) -60 - 60 mv output impedance (guaranteed by design) 0.2khz < f < 03.4khz - 5 20 w 2- to 4-wire (metallic to v tx ) voltage gain 0.3khz < f < 03.4khz (note 14, figure 7) 0.98 1.0 1.02 v/v figure 6. two-wire return loss figure 7. overload level (4-wire transmit port), output offset voltage, 2-wire to 4-wire voltage gain and harmonic distortion 4-wire receive port (rsn) dc voltage i rsn = 0ma - 0 - v r x sum node impedance (guaranteed by design) 0.3khz < f < 3.4khz - - 20 w current gain-rsn to metallic 0.3khz < f < 3.4khz (note 15, figure 8) 980 1000 1020 ratio frequency response (off-hook) 2-wire to 4-wire 0dbm at 1.0khz, e rx = 0v, 0.3khz < f < 3.4khz (note 16, figure 9) -0.2 - 0.2 db 4-wire to 2-wire 0dbm at 1.0khz, e g = 0v, 0.3khz < f < 3.4khz (note 17, figure 9) -0.2 - 0.2 db 4-wire to 4-wire 0dbm at 1.0khz, e g = 0v, 0.3khz < f < 3.4khz (note 18, figure 9) -0.2 - 0.2 db insertion loss 2-wire to 4-wire 0dbm, 1khz (note 19, figure 9) -0.2 - 0.2 db 4-wire to 2-wire 0dbm, 1khz (note 20, figure 9) -0.2 - 0.2 db gain tracking (ref = -10dbm, at 1.0khz) 2-wire to 4-wire -40dbm to +3dbm (note 21, figure 9) -0.1 - 0.1 db 2-wire to 4-wire -55dbm to -40dbm (note 21, figure 9) - 0.03 - db 4-wire to 2-wire -40dbm to +3dbm (note 22, figure 9) -0.1 - 0.1 db electrical speci?ations t a =0 o cto70 o c, v cc =5v 5%, v ee = -5v 5%, v bat = -28v, agnd = bgnd = 0v, r dc1 =r dc2 = 41.2k ? , r d = 39k ? , r sg = , r f1 = r f2 = 0 ? , c hp = 10nf, c dc = 1.5 f, z l = 600 ? . (continued) parameter conditions min typ max units r rx v s 300k ? z d r lr r t 600k ? r r z in v m tip 27 v tx 19 ring 28 rsn 16 r t r rx i dcmet 600k ? 300k ? c e g r l v txo 600 ? z l v tr 23ma 2.16 f v tx tip 27 v tx 19 ring 28 rsn 16 HC5526 5 4-wire to 2-wire -55dbm to -40dbm (note 22, figure 9) - 0.03 - db figure 8. current gain-rsn to metallic figure 9. frequency response, insertion loss, gain tracking and harmonic distortion noise idle channel noise at 2-wire c-message weighting (note 23, figure 10) - 10 - dbrnc idle channel noise at 4-wire c-message weighting (note 24, figure 10) - 10 - dbrnc harmonic distortion 2-wire to 4-wire 0dbm, 1khz (note 25, figure 7) - -65 -54 db 4-wire to 2-wire 0dbm, 0.3khz to 3.4khz (note 26, figure 9) - -65 -54 db battery feed characteristics constant loop current tolerance r dcx = 41.2k ? i l = 2500/(r dc1 + r dc2 ), 0 o c to 70 o c (note 27) 0.9i l i l 1.1i l ma loop current tolerance (standby) i l = (v bat -3)/(r l +1800), 0 o c to 70 o c (note 28) 0.8i l i l 1.2i l ma open circuit voltage (v tip - v ring )0 o c to 70 o c, (active) 14 - 20 v loop current detector on-hook to off-hook r d = 39k ?, 0 o c to 70 o c 372/r d 465/r d 558/r d ma off-hook to on-hook r d = 39k ?, 0 o c to 70 o c 325/r d 405/r d 485/r d ma loop current hysteresis r d = 39k ?, 0 o c to 70 o c 25/r d 60/r d 95/r d ma ground key detector tip/ring current difference - trigger (note 29, figure 11) 8 12 17 ma tip/ring current difference - reset (note 29, figure 11) 3 7 12 ma electrical speci?ations t a =0 o cto70 o c, v cc =5v 5%, v ee = -5v 5%, v bat = -28v, agnd = bgnd = 0v, r dc1 =r dc2 = 41.2k ? , r d = 39k ? , r sg = , r f1 = r f2 = 0 ? , c hp = 10nf, c dc = 1.5 f, z l = 600 ? . (continued) parameter conditions min typ max units r dc2 41.2k ? r dc1 41.2k ? c dc 1.5 f r l 600 ? tip 27 ring 28 r dc 14 rsn 16 r rx 300k ? v rsn = 0v v rsn = -3v grx = ((v tr1 - v tr2 )(300k))/(-3)(600) where: v tr1 is the tip to ring voltage with v rsn = 0v v tr and v tr2 is the tip to ring voltage with v rsn = -3v r t r rx i dcmet 600k ? 300k ? c 1/ c << r l e g r l v tx 600 ? v tr e rx tip 27 v tx 19 ring 28 rsn 16 HC5526 6 hysteresis (note 29, figure 11) 0 5 9 ma figure 10. idle channel noise figure 11. ground key detect ring trip detector (dt, dr) offset voltage source res = 0 -20 - 20 mv input bias current source res = 0 -500 - 500 na input common-mode range source res = 0 v bat +1 - 0 v input resistance source res = 0, balanced 3 - - m ? ring relay driver v sat at 25ma i ol = 25ma - 1.0 1.5 v off-state leakage current v oh = 12v - - 10 a digital inputs (e0, e1, c1, c2) input low voltage, v il 0 - 0.8 v input high voltage, v ih 2-v cc v input low current, i il : c1, c2 v il = 0.4v -200 - - a input low current, i il : e0, e1 v il = 0.4v -100 - - a input high current v ih = 2.4v - - 40 a detector output ( det) output low voltage, v ol i ol = 2ma - - 0.45 v output high voltage, v oh i oh = 100 a 2.7 - - v internal pull-up resistor 10 15 20 k ? power dissipation open circuit state c1 = c2 = 0 - - 23 mw on-hook, standby c1 = c2 = 1 - - 30 mw on-hook, active c1 = 0, c2 = 1, r l = high impedance - - 150 mw off-hook, active r l = 0 ? - - 1.1 w r l = 300 ? - - 0.75 w r l = 600 ? - - 0.5 w temperature guard thermal shutdown 150 - 180 o c electrical speci?ations t a =0 o cto70 o c, v cc =5v 5%, v ee = -5v 5%, v bat = -28v, agnd = bgnd = 0v, r dc1 =r dc2 = 41.2k ? , r d = 39k ? , r sg = , r f1 = r f2 = 0 ? , c hp = 10nf, c dc = 1.5 f, z l = 600 ? . (continued) parameter conditions min typ max units r t r rx 600k ? 300k ? 600 ? v tr v tx r l tip 27 v tx 19 ring 28 rsn 16 tip 27 rsn 16 ring 28 r dc 14 r dc2 41.2k ? r dc1 41.2k ? c dc 1.5 f det e 1 = c 1 = 0, c 2 = 1 HC5526 7 circuit operation and design information the HC5526 is a current feed voltage sense s ubscriber l ine i nterface c ircuit (slic). this means that for short loop applications the slic provides a programmed constant current to the tip and ring terminals while sensing the tip to ring voltage. the following discussion separates the slic s operation into its dc and ac paths, then follows up with additional circuit and design information. constant loop current (dc) path slic in the active mode the dc path establishes a constant loop current that ?ws out of tip and into the ring terminal. the loop current is programmed by resistors r dc1 , r dc2 and the voltage on the r dc pin (figure 13). the r dc voltage is determined by the voltage across r 1 in the saturation guard circuit. under constant current feed conditions, the voltage drop across r 1 sets the r dc voltage to -2.5v. this occurs when current ?ws through r 1 into the current source i 2 . the r dc voltage establishes a current (i rsn ) that is equal to v rdc /(r dc1 +r dc2 ). this current is then multiplied by 1000, in the loop current circuit, to become the tip and ring loop currents. for the purpose of the following discussion, the saturation guard voltage is de?ed as the maximum tip to ring voltage at which the slic can provide a constant current for a given battery and overhead voltage. supply currents (v bat = -28v) i cc , on-hook open circuit state (c1, 2 = 0, 0) - - 1.5 ma standby state (c1, 2 = 1, 1) - - 1.7 ma active state (c1, 2 = 0,1) - - 5.5 ma i ee , on-hook open circuit state (c1, 2 = 0, 0) - - 0.8 ma standby state (c1, 2 = 1, 1) - - 0.8 ma active state (c1, 2 = 0, 1) - - 2.2 ma i bat , on-hook open circuit state (c1, 2 = 0, 0) - - 0.4 ma standby state (c1, 2 = 1, 1) - - 0.6 ma active state (c1, 2 = 0, 1) - - 3.9 ma psrr v cc to 2 or 4-wire port (note 30, figure 12) - 40 - db v ee to 2 or 4-wire port (note 30, figure 12) - 40 - db v bat to 2 or 4-wire port (note 30, figure 12) - 40 - db figure 12. power supply rejection ratio electrical speci?ations t a =0 o cto70 o c, v cc =5v 5%, v ee = -5v 5%, v bat = -28v, agnd = bgnd = 0v, r dc1 =r dc2 = 41.2k ? , r d = 39k ? , r sg = , r f1 = r f2 = 0 ? , c hp = 10nf, c dc = 1.5 f, z l = 600 ? . (continued) parameter conditions min typ max units r t r rx 600k ? 300k ? r l v tx 600 ? 100mv rms , 50hz to 4khz -48v supply 5v supply -5v supply psrr = 20 log (v tx /v in ) tip 27 v tx 19 ring 28 rsn 16 HC5526 8 for loop resistances that result in a tip to ring voltage less than the saturation guard voltage the loop current is defined as: where: i l = constant loop current. r dc1 and r dc2 = loop current programming resistors. capacitor c dc between r dc1 and r dc2 removes the vf signals from the battery feed control loop. the value of c dc is determined by equation 2: where t = 30ms. the minimum c dc value is obtained if r dc1 = r dc2 . figure 14 illustrates the relationship between the tip to ring voltage and the loop resistance. for a 0 ? loop resistance both tip and ring are at v bat /2. as the loop resistance increases, so does the voltage differential between tip and ring. when this differential voltage becomes equal to the saturation guard voltage, the operation of the slic s loop feed changes from a constant current feed to a resistive feed. the loop current in the resistive feed region is no longer constant but varies as a function of the loop resistance. figure 15 shows the relationship between the saturation guard voltage, the loop current and the loop resistance. notice from figure 15 that for a loop resistance <1.2k ? (r sg = 21.4k ? ) the slic is operating in the constant current feed region and for resistances >1.2k ? the slic is operating in the resistive feed region. operation in the resistive feed region allows long loop and off-hook transmission by keeping the tip and ring voltages off the rails. operation in this region is transparent to the customer. the saturation guard circuit (figure 13) monitors the tip to ring voltage via the transconductance ampli?r a 1 . a 1 generates a current that is proportional to the tip to ring voltage difference. i 1 is internally set to sink all of a 1 ? current until the tip to ring voltage exceeds 12.5v. when the tip to ring voltage exceeds 12.5v (with no r sg resistor) a 1 supplies more current than i 1 can sink. when this happens a 2 ampli?s its input current by a factor of 12 and the current through r 1 becomes the difference between i 2 and the output current from a 2 . as the current from a 2 increases, the voltage across r 1 decreases and the output voltage on r dc decreases. this results in a corresponding decrease in the loop current. the r sg pin provides the ability to increase the saturation guard reference voltage beyond 12.5v. equation 3 HC5526 v tx r rx r dc1 r dc2 c dc rsn r dc i rsn tip ring -2.5v i ring i tip a 2 i tip i ring r sg r sg -5v loop current circuit saturation guard circuit a 1 i 1 i 2 r 1 + - + - + - + - -5v figure 13. dc loop current -5v i l 2.5v r dc1 r dc2 + ------------------------------------- - 1000 = (eq. 1) c dc t 1 r dc1 --------------- 1 r dc2 --------------- + ?? ?? = (eq. 2) 0 1.2k -50 -40 -30 -20 -10 0 v bat = -48v, i l = 23ma, r sg = 21.4k ? loop resistance ( ? ) v tip v ring resistive feed region tip to ring voltage (v) constant current feed region saturation guard voltage saturation guard voltage figure 14. v tr vs r l 0 10 20 30 0 10 20 30 40 50 loop current (ma) tip to ring voltage (v) v bat = -24v, r sg = v bat = -48v, r sg = 21.4k ? saturation guard resistive feed region constant current feed region r rsg = 21.4k ? 100k ? 100k ? 4k ? 1.5k ? 2k ? 700 ? <400 ? <1.2k ? r l r l r rsg = ? voltage, v tr = 38v saturation guard voltage, v tr = 13v figure 15. v tr vs i l and r l HC5526 9 gives the relationship between the r sg resistor value and the programmable saturation guard reference voltage: where: v sgref = saturation guard reference voltage, and, r sg = saturation guard programming resistor. when the saturation guard reference voltage is exceeded, the tip to ring voltage is calculated using equation 4: where: v tr = voltage differential between tip and ring, and, r l = loop resistance. for on-hook transmission r l = , equation 4 reduces to: the value of r sg should be calculated to allow maximum loop length operation. this requires that the saturation guard reference voltage be set as high as possible without clipping the incoming or outgoing vf signal. a voltage margin of -4v on tip and -4v on ring, for a total of -8v margin, is recommended as a general guideline. the value of r sg is calculated using equation 6: where: v bat = battery voltage, and v margin = recommended value of -8v to allow a maximum overload level of 3.1v peak . for on-hook transmission r l = , equation 6 reduces to: slic in the standby mode overall system power is saved by con?uring the slic in the standby state when not in use. in the standby state the tip and ring ampli?rs are disabled and internal resistors are connected between tip to ground and ring to v bat . this connection enables a loop current to ?w when the phone goes off-hook. the loop current detector then detects this current and the slic is con?ured in the active mode for voice transmission. the loop current in standby state is calculated as follows: where: i l = loop current in the standby state, r l = loop resistance, and v bat = battery voltage. (ac) transmission path slic in the active mode figure 16 shows a simpli?d ac transmission model. circuit analysis yields the following design equations: where: v tr = is the ac metallic voltage between tip and ring, including the voltage drop across the fuse resistors r f , v tx = is the ac metallic voltage. either at the ground referenced 4-wire side or the slic tip and ring terminals, i m = is the ac metallic current, r f = is a fuse resistor, z t = is used to set the slic s 2-wire impedance, v rx = is the analog ground referenced receive signal, z rx = is used to set the 4-wire to 2-wire gain, e g = is the ac open circuit voltage, and z l = is the line impedance. (ac) 2-wire impedance the ac 2-wire impedance (z tr ) is the impedance looking into the slic, including the fuse resistors, and is calculated as follows: let v rx = 0. then from equation 10: z tr is de?ed as: substituting in equation 9 for v tr : substituting in equation 12 for v tx : v sgref 12.5 510 ? 5 r sg ------------------ + = (eq. 3) v tr r l 16.66 5 10 5 ? r sg ? + r l r dc1 r dc2 + () 600 ? + ---------------------------------------------------------------------- = (eq. 4) v tr 16.66 510 5 ? r sg ------------------ + = (eq. 5) r sg 510 5 ? v bat v margin () 1 r dc1 r dc2 + () 600r l ------------------------------------------ - + ?? ?? ?? 16.66v ------------------------------------------------------------------------------------------------------------------------------- ------------------- = (eq. 6) r sg 510 5 ? v bat v margin 16.66v ---------------------------------------------------------------------------- = (eq. 7) i l v bat 3v r l 1800 ? + ------------------------------- - (eq. 8) v tr v tx i m 2r f ? + = (eq. 9) v tx z t ---------- - v rx z rx ----------- + i m 1000 ------------ - = (eq. 10) v tr e g i m z l ? = (eq. 11) v tx z t i m 1000 ------------ - ? = (eq. 12) z tr v tr i m ----------- = (eq. 13) z tr v tx i m ---------- - 2r f i m ? i m ----------------------- + = (eq. 14) z tr z t 1000 ------------ - 2r f + = (eq. 15) HC5526 10 therefore: equation 16 can now be used to match the slic s impedance to any known line impedance (z tr ). example: calculate z t to make z tr = 600 ? in series with 2.16 f. r f = 20 ? . z t = 560k ? in series with 2.16nf. (ac) 2-wire to 4-wire gain the 2-wire to 4-wire gain is equal to v tx / v tr . from equations 9 and 10 with v rx = 0: (ac) 4-wire to 2-wire gain the 4-wire to 2-wire gain is equal to v tr /v rx . from equations 9, 10 and 11 with e g = 0: for applications where the 2-wire impedance (z tr , equation 15) is chosen to equal the line impedance (z l ), the expression for a 4-2 simpli?s to: (ac) 4-wire to 4-wire gain the 4-wire to 4-wire gain is equal to v tx /v rx . from equations 9, 10 and 11 with e g = 0: transhybrid circuit the purpose of the transhybrid circuit is to remove the receive signal (v rx ) from the transmit signal (v tx ), thereby preventing an echo on the transmit side. this is accomplished by using an external op amp (usually part of the codec) and by the inversion of the signal from the 4-wire receive port (rsn) to the 4-wire transmit port (v tx ). figure 17 shows the transhybrid circuit. the input signal will be subtracted from the output signal if i 1 equals i 2 . node analysis yields the following equation: the value of z b is then: where v rx /v tx equals 1/ a 4-4 . therefore: example: given: r tx = 20k ? , z rx = 280k ? , z t = 562k ? (standard value), r f = 20 ? and z l = 600 ? . the value of z b = 18.7k ? . v tx rsn tip ring i m z tr v tr e g v tx i m 1000 v tx z rx 1 HC5526 r f r f a = 4 + - + - + - + - z t + - v rx + - a = 250 a = 250 i m z l figure 16. simplified ac transmission circuit z t 1000 z tr 2r f () ? = (eq. 16) z t 1000 600 1 j 2.16 ? 10 6 ? ----------------------------------------- 220 ? + ?? ?? ? = a 24 v tx v tr ----------- z t 1000 ? z t 1000 ? 2r f + ----------------------------------------- - == (eq. 17) a 42 v tr v rx ----------- z t z rx ----------- z l z t 1000 ------------ - 2r f z l ++ -------------------------------------------- ? == (eq. 18) a 42 z t z rx ----------- 1 2 -- - ? = (eq. 19) a 44 v tx v rx ----------- z t z rx ----------- z l 2r f + z t 1000 ------------ - 2r f z l ++ -------------------------------------------- ? == (eq. 20) v tx r tx ----------- v rx z b ----------- + 0 = (eq. 21) z b r tx v rx v tx ----------- ? = (eq. 22) z b r tx z rx z t ----------- ? z t 1000 ------------ - 2r f z l ++ z l 2r f + -------------------------------------------- ? = (eq. 23) HC5526 11 supervisory functions the loop current, ground key and the ring trip detector outputs are multiplexed to a single logic output pin called det. see table 1 to determine the active detector for a given logic input. for further discussion of the logic circuitry see section titled ?igital logic inputs? before proceeding with an explanation of the loop current detector, ground key detector and later the longitudinal impedance, it is important to understand the difference between a ?etallic and ?ongitudinal loop currents. figure 18 illustrates 3 different types of loop current encountered. case 1 illustrates the metallic loop current. the de?ition of a metallic loop current is when equal currents ?w out of tip and into ring. loop current is a metallic current. cases 2 and 3 illustrate the longitudinal loop current. the de?ition of a longitudinal loop current is a common mode current, that ?ws either out of or into tip and ring simultaneously. longitudinal currents in the on-hook state result in equal currents ?wing through the sense resistors r 1 and r 2 (figure 18). and longitudinal currents in the off- hook state result in unequal currents ?wing through the sense resistors r 1 and r 2 . notice that for case 2, longitudinal currents ?wing away from the slic, the current through r 1 is the metallic loop current plus the longitudinal current; whereas the current through r 2 is the metallic loop current minus the longitudinal current. longitudinal currents are generated when the phone line is in?enced by magnetic ?lds (e.g., power lines). loop current detector figure 18 shows a simplified schematic of the loop current and ground key detectors. the loop current detector works by sensing the metallic current flowing through resistors r 1 and r 2 . this results in a current (i rd ) out of the transconductance amplifier (gm 1 ) that is equal to the product of gm 1 and the metallic loop current. i rd then flows out the r d pin and through resistor r d to v ee . the value of i rd is equal to: the i rd current results in a voltage drop across r d that is compared to an internal 1.25v reference voltage. when the voltage drop across r d exceeds 1.25v, and the logic is con?ured for loop current detection, the det pin goes low. the hysteresis resistor r h adds an additional voltage effectively across r d , causing the on-hook to off-hook threshold to be slightly higher than the off-hook to on-hook threshold. taking into account the hysteresis voltage, the typical value of r d for the on-hook to off-hook condition is: taking into account the hysteresis voltage, the typical value of r d for the off-hook to on-hook condition is: a ?ter capacitor (c d ) in parallel with r d will improve the accuracy of the trip point in a noisy environment. the value of this capacitor is calculated using the following equation: where: t = 0.5ms. ground key detector a simplified schematic of the ground key detector is shown in figure 18. ground key, is the process in which the ring terminal is shorted to ground for the purpose of signaling an operator or seizing a phone line (between the central office and a private branch exchange). the ground key detector is activated when unequal current flow through resistors r 1 and r 2 . this results in a current (i gk ) out of the transconductance amplifier (gm 2 ) that is equal to the product of gm 2 and the differential (i tip -i ring ) loop current. if i gk is less than the internal current source (i 1 ), then diode d 1 is on and the output of the ground key comparator is low. if i gk is greater than the internal current source (i 1 ), then diode d 2 is on and the output of the ground key comparator is high. with the output of the ground key comparator high, and the logic configured for ground key detect, the det pin goes low. the ground key detector has a built in hysteresis of typically 5ma between its trigger and reset values. ring trip detector ring trip detection is accomplished with the internal ring trip comparator and the external circuitry shown in figure 19. the process of ring trip is initiated when the logic input pins are in the following states: e0 = 0, e1 = 1/0, c1 = 1 and c2 = 0. this logic condition connects the ring trip comparator to the det output, and causes the ringrly pin to energize the ring relay. the ring relay connects the tip and ring of the phone to the external circuitry in figure 19. when the phone is on-hook the dt pin is more positive than the dr pin and the det output is high. for off-hook conditions dr is more positive than dt and det goes low. when det goes low, indicating that the phone has gone off-hook, the slic is commanded by the logic inputs to go into the active state. in the active state, tip and ring are once again connected to the phone and normal operation ensues. HC5526 v tx rsn r tx r fb codec/ filter i 1 i 2 v tx z rx z t + - z b v rx + - + - figure 17. transhybrid circuit i rd i tip i ring 600 ----------------------------------- - i l 300 --------- - == (eq. 24) r d 465 i on hook to off hook -------------------------------------------------------------------------- = (eq. 25) r d 375 i off hook to on hook -------------------------------------------------------------------------- = (eq. 26) c d t r d ------- - = (eq. 27) HC5526 12 figure 19 illustrates battery backed unbalanced ring injected ringing. for tip injected ringing just reverse the leads to the phone. the ringing source could also be balanced. note: the det output will toggle at 20hz because the dt input is not completely ?tered by c rt . software can examine the duty cycle and determine if the det pin is low for more that half the time, if so the off-hook condition is indicated. longitudinal impedance the feedback loop described in figure 20(a, b) realizes the desired longitudinal impedances from tip to ground and from ring to ground. nominal longitudinal impedance is resistive and in the order of 22 ? . in the presence of longitudinal currents this circuit attenuates the voltages that would otherwise appear at the tip and ring terminals, to levels well within the common mode range of the slic. in fact, longitudinal currents may exceed the programmed dc loop current without disturbing the slic s vf transmission capabilities. the function of this circuit is to maintain the tip and ring voltages symmetrically around v bat /2, in the presence of longitudinal currents. the differential transconductance ampli?rs g t and g r accomplish this by sourcing or sinking the required current to maintain v c at v bat /2. when a longitudinal current is injected onto the tip and ring inputs, the voltage at v c moves from it s equilibrium value v bat /2. when v c changes by the amount ? v c , this change appears between the input terminals of the differential transconductance ampli?rs g t and g r . the output of g t and g r are the differential currents ? i 1 and ? i 2 , which in turn feed the differential inputs of current sources i t and i r respectively. i t and i r have current gains of 250 single ended and 500 differentially, thus leading to a change in i t and i r that is equal to 500( ? i ) and 500( ? i 2 ). the circuit shown in figure 20(b) illustrates the tip side of the longitudinal network. the advantages of a differential input current source are: improved noise since the noise due to current source 2i o is now correlated, power savings due to differential current gain and minimized offset error at the operational ampli?r inputs via the two 5k ? resistors. digital logic inputs table 1 is the logic truth table for the ttl compatible logic input pins. the HC5526 has two enable inputs pins (e0, e1) and two control inputs pins (c1, c2). the enable pin e0 is used to enable or disable the det output pin. the det pin is enabled if e0 is at a logic level 0 and disabled if e0 is at a logic level 1. the enable pin e1 gates the ground key detector to the det output with a logic level 0, and gates the loop or ring trip detector to the det output with a logic level 1. a combination of the control pins c1 and c2 is used to select 1 of the 4 possible operating states. a description of each operating state and the control logic follow: open circuit state (c1 = 0, c2 = 0) in this state the slic is effectively off. all detectors and both the tip and ring line drive ampli?rs are powered down, presenting a high impedance to the line. power dissipation is at a minimum. HC5526 det r d r 2 gm 1 gm 2 gm 1 (i metallic ) r d c d v ref + - current loop v ee -5v ground key comparator gm 2 (i tip - i ring ) i rd r h i 1 d 1 d 2 i gk ring tip + - r 1 + - case 1 case 2 case 3 i metallic i longitudinal i longitudinal comparator digital multiplexer + - 1.25v + - r h figure 18. loop current and ground key detectors tip ring HC5526 r rt v bat e rg r 3 r 4 r 2 r 1 dr dt ring trip comparator det c rt ringrly ring relay + - figure 19. ring trip circuit for battery backed ringing HC5526 13 active state (c1 = 0, c2 = 1) the tip output is capable of sourcing loop current and for open circuit conditions is about -4v from ground. the ring output is capable of sinking loop current and for open circuit conditions is about v bat +4v. vf signal transmission is normal. the loop current and ground key detectors are both active, e0 and e1 determine which detector is gated to the det output. ringing state (c1 = 1, c2 = 0) the ring relay driver and the ring trip detector are activated. both the tip and ring line drive ampli?rs are powered down. both tip and ring are disconnected from the line via the external ring relay. standby state (c1 = 1, c2 = 1) both the tip and ring line drive amplifiers are powered down. internal resistors are connected between tip to ground and ring to v bat to allow loop current detect in an off-hook condition. the loop current and ground key detectors are both active, e0 and e1 determine which detector is gated to the det output. ac transmission circuit stability to ensure stability of the ac transmission feedback loop two compensation capacitors c tc and c rc are required. figure 21 (application circuit) illustrates their use. recommended value is 2200pf. ac-dc separation capacitor, c hp the high pass ?ter capacitor connected between pins hpt and hpr provides the separation between circuits sensing tip to ring dc conditions and circuits processing ac signals. a 10nf c hp will position the low end frequency response 3db break point at 48hz. where: where r hp = 330k ? . thermal shutdown protection the HC5526 |